The present invention relates generally to digital clock circuits. More particularly, the present invention relates to a clock phase generator circuit that provides a number of phase-delayed clock signals generated in response to an input clock signal.
Clock phase generator circuits provide different clock phases based upon an input clock signal. For example, certain applications require a set of clock phases that are evenly distributed across one clock period. One conventional design for a clock phase generator employs a number of voltage-controlled phase delay elements connected in series such that the input clock signal is increasingly delayed as it propagates through the delay elements. Ideally, the series of phase delay elements is designed to provide an overall phase delay equal to 180 degrees, and inverted versions of the delayed clock signals provide delay values between 180 and 360 degrees. However, in practical implementations, a precise 180 degree delay cannot be guaranteed due to the imprecise nature of the control voltage applied to the delay elements. Furthermore, the load experienced by each phase delay element may not be identical. These effects can result in a set of unevenly distributed phase delayed signals with varied amplitude characteristics. Furthermore, for differential clock phase signals, a long string of delay elements without feedback may result in an accumulation of common-mode voltage offset between the positive and negative differential signal components. Such an accumulation of offset voltage can distort or corrupt the clock phase signals. Consequently, this prior art configuration may not be suitable in applications that require precise phase delay spacing throughout a clock period.
A clock phase generator circuit according to the invention utilizes a loop-back path from the output of the last phase delay element to the input of the first phase delay element. The circuit is configured such that each of the phase delay elements are equally loaded, which equalizes the phase intervals and the amplitude of the generated clock signals. The circuit configuration, along with the loop-back path, enables the circuit to accurately provide a number of clock signals that have evenly distributed phase delays relative to the input clock signal.
The above and other aspects of the present invention may be carried out in one form by a clock phase generator circuit comprising a first node for receiving an input clock signal, a second node for receiving a control signal, a plurality of phase delay elements coupled in series, where at least one of the phase delay elements is coupled to the input node, and where each phase delay element provides a respective phase delay that is determined by the control signal, and a loop-back path between an output of one of the phase delay elements and the first node. The phase delay elements provide a number of output clock signals having different phase delays, relative to the input clock signal.